1. Field of the Invention
This invention is related to the field of microprocessors and, more particularly, to prefetch instructions within microprocessors.
2. Description of the Related Art
Superscalar microprocessors achieve high performance by executing multiple instructions per clock cycle and by choosing the shortest possible clock cycle consistent with the design. On the other hand, superpipelined microprocessor designs divide instruction execution into a large number of subtasks which can be performed quickly, and assign pipeline stages to each subtask. By overlapping the execution of many instructions within the pipeline, superpipelined microprocessors attempt to achieve high performance.
Superscalar microprocessors demand low memory latency due to the number of instructions attempting concurrent execution and due to the increasing clock frequency (i.e. shortening clock cycle) employed by the superscalar microprocessors. Many of the instructions include memory operations to fetch (read) and update (write) memory operands. The memory operands must be fetched from or conveyed to memory, and each instruction must originally be fetched from memory as well. Similarly, superpipelined microprocessors demand low memory latency because of the high clock frequency employed by these microprocessors and the attempt to begin execution of a new instruction each clock cycle. It is noted that a given microprocessor design may employ both superscalar and superpipelined techniques in an attempt to achieve the highest possible performance characteristics.
Microprocessors are often configured into computer systems which have a relatively large, relatively slow main memory. Typically, multiple dynamic random access memory (DRAM) modules comprise the main memory system. The large main memory provides storage for a large number of instructions and/or a large amount of data for use by the microprocessor, providing faster access to the instructions and/or data than may be achieved from a disk storage, for example. However, the access times of modern DRAMs are significantly longer than the clock cycle length of modern microprocessors. The memory access time for each set of bytes being transferred to the microprocessor is therefore long. Accordingly, the main memory system is not a low latency system. Microprocessor performance may suffer due to high memory latency.
In order to allow low latency memory access (thereby increasing the instruction execution efficiency and ultimately microprocessor performance), computer systems typically employ one or more caches to store the most recently accessed data and instructions. Additionally, the microprocessor may employ caches internally. A relatively small number of clock cycles may be required to access data stored in a cache, as opposed to a relatively larger number of clock cycles required to access the main memory.
Low memory latency may be achieved in a computer system if the cache hit rates of the caches employed therein are high. An access is a hit in a cache if the requested data is present within the cache when the access is attempted. On the other hand, an access is a miss in a cache if the requested data is absent from the cache when the access is attempted. Cache hits are provided to the microprocessor in a small number of clock cycles, allowing subsequent accesses to occur more quickly as well and thereby decreasing the effective memory latency. Cache misses require the access to receive data from the main memory, thereby increasing the effective memory latency.
In many performance critical applications, large data sets are manipulated. For example, floating point intensive applications often operate upon two or three dimensional arrays holding 4 to 20 megabytes of data. A repetitive set of operations may be performed upon the elements within the arrays, generating a fixed number of references to each datum (after which the datum may not be accessed for a relatively long period of time). Accordingly, it would be desirable to store the data being referenced in registers until the fixed number of references are performed, then discard that data in favor of the next data to be referenced. If enough registers are available to the compiler, code may be generated in this manner. Unfortunately, when the number of registers available for storing the data is limited (e.g. in the x86 architecture), the data often cannot be held in the registers until the fixed number of accesses occur. Furthermore, the data set being operated upon (e.g. 4 to 20 megabytes) is substantially larger than the typical cache size included in microprocessors. Data may be overwritten within the cache prior to occurrence of the fixed number of references to that data. Still further, after the last access to the data, data may be retained in the cache while other, less recently accessed data is replaced. Accordingly, cache misses and long memory latencies may be regularly experienced by these performance critical applications, thereby reducing performance of the microprocessor when executing these applications.